1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to P-channel transistors comprising a high-k metal gate electrode formed in an early manufacturing stage.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which represent the dominant circuit element in complex integrated circuits. For example, several hundred millions of transistors may be provided in presently available complex integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity, in combination with a desired channel controllability.
Upon continuously reducing the channel length of field effect transistors, generally, an increased degree of capacitive coupling is required in order to maintain controllability of the channel region, which may typically require an adaptation of a thickness and/or material composition of the gate dielectric material. For example, for a gate length of approximately 80 nm, a gate dielectric material based on silicon dioxide with a thickness of less than 2 nm may be required in high speed transistor elements, which may, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may increasingly become incompatible with thermal power requirements of sophisticated integrated circuits, other alternatives have been developed in increasing the charge carrier mobility in the channel region, thereby also enhancing overall performance of field effect transistors. One promising approach in this respect is the generation of a certain type of strain in the channel region, since the charge carrier mobility in silicon strongly depends on the strain conditions of the crystalline material. For example, for a standard crystallographic configuration of the silicon-based channel region, a compressive strain component in a P-channel transistor may result in a superior mobility of holes, thereby increasing switching speed and drive current of P-channel transistors. The desired compressive strain component may be obtained according to well-established approaches by incorporating a strain-inducing semiconductor material, for instance in the form of a silicon/germanium mixture or alloy, in the active region of the P-channel transistor. For example, after forming the gate electrode structure, corresponding cavities may be formed laterally adjacent to the gate electrode structure in the active region and may be refilled with the silicon/germanium alloy which, when grown on the silicon material, may have an internal strained state, which in turn may induce a corresponding compressive strain component in the adjacent channel region.
During the continuous reduction of the critical dimensions of transistors, an appropriate adaptation of the material composition of the gate dielectric material has been proposed such that, for a physically appropriate thickness of a gate dielectric material, i.e., for reducing the gate leakage currents, a desired high capacitive coupling may nevertheless be achieved. Thus, material systems have been developed which have a significantly higher dielectric constant, compared to the conventionally used silicon dioxide-based materials, silicon oxynitride materials and the like. For example, materials including hafnium, zirconium, aluminum and the like may have a significantly higher dielectric constant and are, therefore, referred to as high-k dielectric materials, which are to be understood as materials having a dielectric constant of 10.0 or higher when measured in accordance with typical measurement techniques. As is well known, the electronic characteristics of the transistor elements also strongly depend on the work function of the gate electrode material, which influences the band structure of the semiconductor material in the channel region separated from the gate electrode material by the gate dielectric material. In well-established polysilicon/silicon dioxide-based gate electrode structures, the corresponding threshold voltage, strongly influenced by the gate dielectric material and the adjacent electrode material, is adjusted by appropriately doping the polysilicon material in order to appropriately adjust the work function of the polysilicon material at the interface between the gate dielectric material and the electrode material. Similarly, in gate electrode structures including a high-k gate dielectric material, the work function has to be appropriately adjusted for N-channel transistors and P-channel transistors, respectively, which may require appropriately selected work function adjusting metal species, such as lanthanum for N-channel transistors and aluminum for P-channel transistors. For this reason, corresponding metal-containing conductive materials may be positioned close to the high-k gate dielectric material in order to form an appropriately designed interface that results in the target work function of the gate electrode structure. In many conventional approaches, the work function adjustment may be performed at a very late manufacturing stage, i.e., after any high temperature processes, which may require the replacement of a placeholder material of the gate electrode structures, such as polysilicon, and the incorporation of appropriate work function adjusting species in combination with an electrode metal, such as aluminum and the like. In this case, however, very complex patterning and deposition process sequences may be required on the basis of gate electrode structures having critical dimensions of 50 nm and significantly less, which may result in severe variations of the resulting transistor characteristics.
Therefore, other process strategies have been proposed in which the work function adjusting materials may be applied in an early manufacturing stage, i.e., upon forming the gate electrode structures, wherein the corresponding metal species may be thermally stabilized and encapsulated in order to obtain the desired work function and thus threshold voltage of the transistors without being unduly influenced by the further processing.
Consequently, process techniques have been developed in which superior gate electrode structures on the basis of a high-k dielectric material may be implemented together with efficient strain-inducing mechanisms, such as a silicon/germanium alloy material, incorporated in the drain and source regions in an attempt to further enhance overall device performance. It turns out, however, that these mechanisms may interact with each other, thereby resulting in a less pronounced gain of performance or even in a reduced overall performance compared to sophisticated P-channel transistors in which only one of these mechanisms is implemented. With reference to FIGS. 1a-1d, a conventional process strategy will be described in more detail so as to more clearly demonstrate the problems associated with the incorporation of a strain-inducing silicon/germanium alloy in the presence of an appropriately encapsulated high-k metal gate electrode structure.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 and a silicon-based semiconductor layer 102, which in turn comprises semiconductor regions or active regions 102A, 102B. It should be appreciated that the active regions 102A, 102B may be laterally delineated by isolation structures (not shown), such as shallow trench isolations. Moreover, in the manufacturing stage shown, the device 100 comprises a P-channel transistor 150A and an N-channel transistor 150B. In this manufacturing stage, the transistors 150A, 150B comprise gate electrode structures 160A, 160B, respectively, each of which included a gate dielectric material 161 that is formed on the basis of a high-k dielectric material. For example, the gate dielectric materials may comprise a dielectric base layer, such as a silicon oxide base material in combination with a high-k dielectric material, such as hafnium oxide and the like. Moreover, the gate electrode structure 160A comprises a metal-containing electrode material 162A, possibly in combination with a work function adjusting metal species, such as aluminum and the like. In other cases, the work function adjusting metal species may be incorporated in the dielectric material 161, depending on the overall process strategy. Similarly, the gate electrode structure 160B comprises an electrode metal 162B, possibly having incorporated therein an appropriate work function metal species, such as lanthanum, while in other cases the work function metal species may be incorporated in the dielectric material 161. Moreover, both electrode structures 160A, 160B comprise a semiconductor-based electrode material 163, such as amorphous silicon, polysilicon and the like. Finally, a dielectric cap material 164 is provided in both gate electrode structures. Furthermore, a protective spacer element 103 is formed on sidewalls of the gate electrode structures 160A, 160B followed by a further spacer 104 which may act as an etch stop material upon removing the dielectric cap material 164 in a later manufacturing stage. It should be appreciated that the spacer element 103, typically comprised of silicon nitride, may be used to maintain integrity of the sensitive materials 161 and 162A, 162B after patterning the gate electrode structures 160A, 160B. In particular, any interaction with aggressive chemicals may be reduced, such as sulfuric acid in combination with hydrogen peroxide and the like, which may frequently be used during the further processing. Additionally, in the manufacturing stage shown, a spacer element 105S is formed on the sidewalls of the gate electrode structure 160A, while a spacer layer 105 covers the active region 102B and the gate electrode structure 160B
Furthermore, the active region 102A may comprise a strain-inducing semiconductor alloy 151, such as a silicon/germanium alloy, in order to provide a desired strain component, i.e., in the example shown, a compressive strain component in the channel region 152. Furthermore, in some cases, a different band structure may be required at the interface between the channel region 152 and the dielectric material 161 in order to appropriately adapt the threshold voltage of the transistor 150A, which may be accomplished by providing a silicon/germanium material 152A and the like.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of well-established and sophisticated process techniques in the following manner. After providing the active regions 102A, 102B, for instance based on isolation structures, the optional material 152A, if required, may be selectively formed in the active region 102A, for instance on the basis of epitaxial growth techniques. Thereafter, the material system for at least the layers 161 and 162A, 162B may be formed by any appropriate deposition or other process techniques, wherein also the required work function adjusting metal species, such as aluminum, lanthanum and the like, may be incorporated in the materials 162A, 162B and/or the dielectric materials 161, for instance by initiating diffusion based on an anneal process and the like. For this purpose, a plurality of different process strategies may be applied. Thereafter, the material 163 may be formed, for instance by low pressure chemical vapor deposition (CVD), followed by the deposition of the dielectric cap material 164, which may include two or more individual material layers, if required. Additionally, any other materials, such as hard mask materials and the like, may be deposited, as required by the following patterning process. Based on complex lithography and etch techniques, the gate electrode structures 160A, 160B are formed in accordance with the design rules of the device 100, thereby obtaining a gate length, i.e., in FIG. 1a, the horizontal extension of the gate electrode structures 160A, 160B, of 40 nm and less. Since the threshold voltage of the transistors 150A, 150B is substantially determined by the configuration of the channel region 152 in combination with the materials 161 and 162A, 162B, any significant modification, in particular of the materials 161 and 162A, 162B, is to be avoided during the further processing. Consequently, a liner material, such as a silicon nitride material, may be deposited and may be patterned into the spacer element 103. Additionally, the spacer 104, for instance in the form of an oxide material, may be formed by depositing an oxide layer and patterning the same into the spacer element 104. Typically, a width of the spacer 103 may be in the range of 3 nm and less in sophisticated applications, wherein, however, a further reduction in spacer width may result in reduced production yield due to undue modification of the materials 161, 162A, 162B. Similarly, the spacer element 104 may have a certain width, for instance in the range of 5-10 nm, so as to act as an efficient etch stop material in a further advanced manufacturing stage. Thereafter, the spacer layer 105 is formed, for instance, by well-established low pressure CVD techniques, thereby providing a thermally stable and moderately dense silicon nitride material, which may provide the desired etch resistivity during the subsequent processing. The spacer layer 105 is then selectively patterned into the spacer element 105S by providing an etch mask, such as a resist mask, above the active region 102B while exposing the transistor 150A and thus the spacer layer 105 to an anisotropic etch atmosphere. Thus the width of the spacer element 105S, which may be in the range of 8-10 nm in sophisticated applications, is substantially determined by the initial thickness of the spacer layer 105 and the parameters of the subsequent plasma assisted etch process, which may have a certain lateral etch rate. Based on the spacer element 105S, the processing is continued by etching into the active region 102A, thereby using the dielectric cap layer 164 and the spacer element 105S as an etch mask. During this anisotropic etch process, the lateral offset of the resulting cavities from the gate electrode structure 160A is, therefore, substantially determined by the combined width of the spacers 103, 104 and 105S. Hence, upon refilling the cavities with the strain-inducing semiconductor alloy 151, the lateral offset of the material 151 is thus determined by the spacers 103, 104 and 105S.
It should be appreciated that the resulting compressive strain component in the channel region 152 is affected by the internal strain component of the material 151, which in turn is determined by the germanium concentration of the silicon/germanium alloy. Since the germanium concentration may not be arbitrarily increased based on available selective epitaxial growth techniques unless creating severe crystal faults, and since the amount of the material 151 is substantially determined by the overall configuration of the transistor 150A, for instance in terms of a thickness of the semiconductor layer 102, the lateral offset of the material 151 is an important factor in increasing the strain and thus performance of the transistor 150A. Consequently, the additional lateral offset caused by the spacer elements 103 and 104, compared to sophisticated approaches, without requiring encapsulation of the gate electrode structure 160A, may result in a significantly reduced strain in the channel region 152.
FIG. 1b schematically illustrates the device 100 in a further advanced manufacturing stage. As illustrated, the gate electrode structures 160A, 160B are laterally confined by the protective spacer elements 103, while the spacers 105S and 104, as well as the spacer layer 105 and the dielectric cap materials 164 (FIG. 1a) have been removed on the basis of an etch sequence using, for instance, hot phosphoric acid for removing silicon nitride materials, wherein the spacer 104 may provide the integrity of the protective spacer elements 103. Thereafter, the spacer 104 may be removed by performing a wet chemical etch process based on hydrofluoric acid (HF).
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. In this stage, the transistors 150A, 150B comprise an offset spacer element 153 in combination with a spacer structure 156, which may be used for forming drain and source regions 157 so as to obtain the desired vertical and lateral dopant profile. For this purpose, well-established process strategies, including the deposition of silicon nitride-based materials on the basis of low pressure CVD techniques, in combination with the deposition of any etch stop liners (not shown), may be applied, while at the corresponding stages, implantation processes are also performed so as to incorporate the drain and source dopant species, possibly in combination with any counter-doping species, as required for adjusting the final transistor characteristics, such as the off current of the transistors and the like. Finally, an anneal process 107 may be performed to activate the dopants in the drain and source regions 157, thereby also adjusting the final dopant profile due to a certain degree of dopant diffusion.
As a consequence, although superior performance of the transistor 150B may be obtained on the basis of the gate electrode structure 160B, a significantly less pronounced gain in performance may be observed for the transistor 150A, although implementing therein the strain-inducing mechanism in the form of the material 151, due to a significantly increased lateral offset of this material 151 from the channel region 152.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.